Hynix_H5TQ2G8(6)3BFR(Rev1.7)

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2Gb DDR3 SDRAM 2Gb DDR3 SDRAM Lead-Free&Halogen-Free (RoHS Compliant) H5TQ2G83BFR-xxC H5TQ2G83BFR-xxI H5TQ2G63BFR-xxC H5TQ2G63BFR-xxI * Hynix Semiconductor reserves the right to change products or specifications without notice. Rev. 1.7 / Dec. 2010 1 Revision History Revision No. 0.1 0.2 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 History Initial Release Added IDD Specification Add supported CL5 Modify the package outline with x16 Low power added M8 pin ball out update Added 1866 speed Suppport Added 2
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  Rev. 1.7 / Dec. 20101 2Gb DDR3 SDRAM 2Gb DDR3 SDRAM Lead-Free&Halogen-Free (RoHS Compliant)  H5TQ2G83BFR-xxCH5TQ2G83BFR-xxIH5TQ2G63BFR-xxCH5TQ2G63BFR-xxI * Hynix Semiconductor reserves the right to change products or specifications without notice.  Rev. 1.7 / Dec. 20102 Revision History Revision No.HistoryDraft DateRemark 0.1Initial ReleaseDec. 20090.2Added IDD SpecificationFeb. 20101.0Add supported CL5Jun. 20101.1Modify the package outline with x16Jun. 20101.2Low power addedSep. 20101.3M8 pin ball out updateSep. 20101.4Added 1866 speed SuppportNov. 20101.5Added 2133 speed SuppportDec. 20101.6Added IDD Specification(2133 speed)Dec. 20101.7Modify OPERATING FREQUENCY TableDec. 2010  Rev. 1.7 / Dec. 20103 Description The H5TQ2G83BFR and H5TQ2G63BFR are a 2,147,483,648-bit CMOS Double Data Rate III (DDR3) Syn-chronous DRAM, ideally suited for the main memory applications which requires large memory density andhigh bandwidth. Hynix 2Gb DDR3 SDRAMs offer fully synchronous operations referenced to both rising andfalling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the CK), Data, Data strobes and Write data masks inputs are sampled on both rising andfalling edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high band-width. Device Features and Ordering Information FEATURES * This product in compliance with the RoHS directive. ã VDD=VDDQ=1.5V +/- 0.075Vã Fully differential clock inputs (CK, CK) operationã Differential Data Strobe (DQS, DQS)ã On chip DLL align DQ, DQS and DQS transition with CK   transitionã DM masks write data-in at the both rising and falling  edges of the data strobeã All addresses and control inputs except data,  data strobes and data masks latched on the  rising edges of the clock ã Programmable CAS latency 5, 6, 7, 8, 9, 10, 11, 12, 13and 14 supportedã Programmable additive latency 0, CL-1, and CL-2  supportedã Programmable CAS Write latency (CWL) = 5, 6, 7, 8, 9,10ã Programmable burst length 4/8 with both nibble  sequential and interleave modeã BL switch on the flyã 8banksã Average Refresh Cycle (Tcase of  0 o C~ 95 o C) - 7.8 µs at 0 o C ~ 85 o C- 3.9 µs at 85 o C ~ 95 o C  Commercial Temperature ( 0 o C~ 85 o C)  Industrial Temperature ( -40 o C~ 85 o C) ã Auto Self Refresh supportedã JEDEC standard 82ball FBGA(x8), 96ball FBGA (x16)ã Driver strength selected by EMRSã Dynamic On Die Termination supportedã Asynchronous RESET pin supportedã ZQ calibration supportedã TDQS (Termination Data Strobe) supported (x8 only)ã Write Levelization supportedã 8 bit pre-fetch  Rev. 1.7 / Dec. 20104 ORDERING INFORMATION * xx means Speed Bin Grade OPERATING FREQUENCY * xx means Speed Bin Grade Part No.ConfigurationPower ConsumptionTemperaturePackage H5TQ2G83BFR-*xxC256M x 8Normal ConsumptionCommercial82ball FBGA H5TQ2G83BFR-*xxIIndustrialH5TQ2G63BFR-*xxC128M x 16Normal ConsumptionCommercial96ball FBGA H5TQ2G63BFR-*xxIIndustrial SpeedGrade(Marking)Frequency [MHz]Remark(CL-tRCD-tRP)CL5CL6CL7CL8CL9CL10CL11CL12CL13CL14 -G7OOOODDR3-1066 7-7-7-H9OOOOOODDR3-1333 9-9-9-PBOOOOOOODDR3-1600 11-11-11-RDOOOOODDR3-1866 13-13-13-TEOOOOOOOOOODDR3-2133 14-14-14
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